The present invention relates to a method of manufacturing a multi-chip package having at least two IC chips mounted on a substrate.
A conventional multi-chip package of this type is designed such that a plurality of IC chips are mounted on a substrate having a wiring pattern formed thereon, and the wiring pattern and the IC chips are connected to each other by wire bonding. Ceramic substrates are often used. However, silicon substrates are sometimes used in consideration of heat dissipation and low stress to IC chips.
FIGS. 4A to 4C show a sequence of steps in a conventional method of manufacturing a multi-chip package.
As shown in FIG. 4A, die-attached metallized layers (metal layers constituting IC chip mounting portions) 2 and a wiring pattern 7 are formed at three positions on a silicon substrate 1. The die-attached metallized layers 2 are directly formed on the silicon substrate 1 so as to be electrically connected thereto. In addition, the wiring pattern 7 is formed in the entire region on the silicon substrate 1 except for portions corresponding to the die-attached metallized layers 2 through an SiO.sub.2 or Si.sub.3 N.sub.4 insulating film.
As shown in FIG. 4B, IC chips 3 are bonded (die-bonded) to the surfaces of the die-attached metallized layers 2. In this bonding step, an epoxy resin is widely used as a bonding material in consideration of a reduction in cost and stress to the IC chips. However, in consideration of a decrease in heat and resistance of the IC chips and electric conduction between the IC chips 3 and the silicon substrate 1, an Au-Si eutectic alloy is generally used for bonding.
Subsequently, as shown FIG. 4C, the respective IC chips 3 and the wiring pattern 7 are connected to each other by using bonding wires 5. Thereafter, the silicon substrate 1 is subjected to encapsulation and the like to manufacture a multi-chip package.
In the conventional method of manufacturing a multi-chip package, however, the wiring pattern 6 must be formed on the substrate in addition to the die-attached metallized layers 2 prior to die bonding of the IC chips 3. For this reason, the manufacturing period of a substrate is undesirably prolonged, and the cost is increased. In addition, when a modification of the wiring pattern is required, a new substrate must be formed again.
In addition, when die bonding of the IC chips 3 are to be performed by an Au-Si eutectic alloy method, since a heating temperature exceeds 400.degree. C., an organic material and a resin material cannot be used as an insulating material.
Moreover, in the conventional method of manufacturing a multi-chip package, the level difference between the die-attached metallized layer 2 and the wiring pattern 7 is small, and the level difference between the IC chip 3 and the wiring pattern 7 is large. For this reason, it is difficult to ensure the ideal shape of the bonding wire 5. Such a drawback may be eliminated by polishing the lower surface of each IC chip 3 or denting the lower surface of each IC chip 3. In this case, however, the manufacturing yield of multi-chip packages is decreased.